I. Field of the Invention
This invention relates to a semiconductor device and a complementary type silicon gate field effect semiconductor in which P-and N-channel type silicon gate field effect transistors are formed on the same substrate.
II. Description of the Prior Art
In a complementary type silicon gate field effect semiconductor integrated circuit device (hereinafter referred to as a silicon gate CMOS.IC), the threshold voltages of P channel and N channel type field effect transistors are so set as to satisty the requirements as to the threshold voltage of the circuit, operation speed, power consumption etc. Usually, the threshold voltages of the transistors are lowered to a range of 0.8 to 2.0 volts within which the lower power consumption property of the CMOS.IC, is not affected.
An impurity of predetermined conductivity type is doped into the channel region (i.e. channel doping) below the gate electrode of each transistor to control the impurity concentration of the channel region of each transistor. In this way, the threshold voltages of transistors are controlled to a desired value. For example, an island-like P-type region is conventionally formed in an N-type silicon substrate and an impurity, such as phosphorus, is doped by channel doping in that portion of an island-like P-type regin and of N-type silicon substrate where a channel region of the transistor is formed. In this way, channel doped layers are formed. Then, an impurity, such as boron, is doped in the N-type silicon substrate to form source and drain regions. In this case, a gate oxide film on that portion of the semiconductor structure corresponding to the channel region and polycrystalline silicon layer overlying the gate oxide film are used as a mask for diffusion. Thus, a P-channel type silicon gate field effect transistor is formed. Likewise, an impurity such as phos-phosphorus is doped into the island-like P-type region with the gate oxide film and polycrystalline silicon layer as a mask to form source and drain regions. Thus, an N-channel type silicon gate field effect transistor is formed.
If the thickness of the gate oxide film, fixed positive charge, and impurity concentration of the polycrystalline silicon layer are determined, then the threshold voltage of the respective transistors is unconditionally determined by the impurity concentration of regions (i.e. island-like P-and N-type regions) in which each transistor is formed. Since the channel doped layer is formed to shift the threshold voltage of the respective transistors to a desired level, impurities at a specified concentration are doped in the channel region. It is advantageous from the standpoint of manufacturing considerations to simultaneously form channel doped layers, but the conventional method has the following disadvantages.
Suppose that the threshold voltage of each transistor is controlled to a reasonable value of, for example, .+-.1.0 volts. If in this case the threshold voltage of both P-and N-channel transistors are to be simultaneously controlled by a one channel doping operation, it is necessary that the impurity concentration of a N-type silicon substrate (i.e. a substrate region of a P-channel type silicon gate field effect transistor) be, for example, about 2.times.10.sup.15 atoms/cm.sup.3 and that the impurity concentration of an island-like P-type region (i.e. substrate region of an N-channel type silicon gate field effect transistor) be a higher value of, for example, about 1.times.10.sup.16 atoms/cm.sup.3. Otherwise it is impossible to simultaneously control the threshold voltages of both transistors. This fact can be seen from FIG. 1 which shows the relationship between the threshold voltage of each transistor and the impurity concentration of the regions in which each transistor is formed.
Since in this way the impurity concentration of the substrate becomes higher, the junction capacitance of source and drain regions of the transistor, as well as the substrate bias effect becomes great. If a random access memory, for example, is constructed using such silicon gate CMOS.IC, a slower access time is involved.
Furthermore, since the polycrystalline silicon layer which serves as a mask in the formation of source and drain regions of each transistor is doped with an impurity of different conductivity type, a direct mutual connection of the polycrystalline silicon layers can not be effected and must be made through an aluminum connection, thus lowering an integration density.